This invention relates to electrical interconnection of integrated circuit chips and, particularly, to interconnection of assemblies including one or more integrated circuit chips.
Interconnection of stacked die with the substrate presents a number of challenges.
Some die as provided have die pads along one or more of the die margins, and these may be referred to as peripheral pad die. Other die as provided have die pads arranged in one or two rows near the center of the die, and these may be referred to as center pad die. The die may be “rerouted” to provide a suitable arrangement of interconnect pads at or near one or more of the margins of the die.